A high-speed serial interface often includes transmitting data at high speeds via one channel. Typically, in the high-speed serial interface, only a data channel is used and a channel by which a clock signal is transmitted is not allocated. Using this method, the number of transmission channels may be reduced. In this case, a clock data recovery circuit may perform phase synchronization to start data transmission after frequency synchronization is performed by a receiver. The clock data recovery circuit may be used to generate a sampling clock signal in synchronization with the phase of data.
In order to reduce power consumption in a timing controller chip that uses a high-speed serial interface (namely, a TCON chip), the supply of power to a communication circuit may be stopped during a period of time when video data such as a still image is not transmitted. When this method is used, the timing controller may be required to start data transmission immediately after the timing controller is powered on.